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_______________ge ne ra l de sc ript ion the max114/max118 are microprocessor-compatible, 8-bit, 4-channel and 8-channel analog-to-digital co n- verters (adcs). they operate from a single +5v supp ly and use a half-flash technique to achieve a 660ns c on- version time (1msps). a power-down ( pwrdn ) pin reduces current consumption typically to 1a. the devices return from power-down mode to normal oper- ating mode in less than 200ns, allowing large suppl y- current reductions in burst-mode applications (in b urst mode, the adc wakes up from a low-power state at specified intervals to sample the analog input sign als). both converters include a track/hold, enabling the adc to digitize fast analog signals. microprocessor (p) interfaces are simplified becau se the adc can appear as a memory location or i/o port wit hout external interface logic. the data outputs use latc hed, three-state buffer circuitry for direct connection to an 8-bit parallel p data bus or system input port. the max114/max118 input/reference configuration enables ratiometric operation. the 4-channel max114 is available in a 24-pin dip o r ssop. the 8-channel max118 is available in a 28-pin dip or ssop. for +3v applications, refer to the max113/max117 data sheet. ________________________applic a t ions high-speed dsp remote data acquisition portable equipment communications systems ____________________________fe a t ure s ? single +5v supply operation ? 4 (max114) or 8 (max118) analog input channels ? low power: 40mw (operating mode) 5w (power-down mode) ? total unadjusted error 1lsb ? fast conversion time: 660ns per channel ? no external clock required ? internal track/hold ? 1mhz full-power bandwidth ? internally connected 8th channel monitorsreference voltage (max118) m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n ________________________________________________________________ maxim integrated products 1 4-bit dac 4-bit flash adc (4msbs) 4-bit flash adc (4lsbs) timing and control address latch decode ref+ 16 three- state output drivers d7 d6 d5 d4 d3 d2 d1 d0 mux *in7 *in8 s ref+ *in6 *in5 in4 in3 in2 in1 a0 a1 a2 ref- pwrdn rd mode int wr/rdy cs max114/max118 * max118 only ___________________________________________________ ______func t iona l dia gra m 19-1083; rev 1; 8/96 part max114 cng max114cag max114c/d 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 24 narrow plastic dip 24 ssop dice* ______________orde ring i nform a t ion for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 max114eng max114eag max114mrg -55c to +125c -40c to +85c -40c to +85c 24 narrow plastic dip 24 ssop 24 narrow cerdip** ordering information continued on last page. *dice are specified at t a = +25c, dc parameters only. **contact factory for availability. pin configurations appear on last page. downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +5v 5%, ref+ = 5v, ref- = gnd, read mode (mode = gnd), t a = t min to t max , unless otherwise noted.) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. v dd to gnd ............................................. .................-0.3v to +7v digital input voltage to gnd ......................- 0.3v to (v dd + 0.3v) digital output voltage to gnd ...................-0. 3v to (v dd + 0.3v) ref+ to gnd........................................ ......-0.3v to (v dd + 0.3v) ref- to gnd........................................ .......-0.3v to (v dd + 0.3v) in_ to gnd ......................................... ........-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70c) 24-pin narrow plastic dip (derate 13.33mw/c above +70c).................... ................1.08w 24-pin ssop (derate 8.00mw/c above +70c)......... .....640mw 24-pin narrow cerdip (derate 12.50mw/c above +70c) .................... .....................1w 28-pin wide plastic dip (derate 14.29mw/c above +70c).................... ................1.14w 28-pin ssop (derate 9.52mw/c above +70c)......... .....762mw 28-pin wide cerdip (derate 16.67mw/c above +70c).................... ................1.33w operating temperature ranges max114/max118c_ _.................................. .........0c to +70c max114/max118e_ _.................................. ......-40c to +85c max114/max118m_ _ .................................. ...-55c to +125c storage temperature range .......................... ...-65c to +150c lead temperature (soldering, 10sec) ................ .............+300c v in _ = 5vp-p max11_m, f sample = 740khz, f in _ = 195.7khz gnd < v in _ < v dd max11_c/e, f sample = 1mhz, f in _ = 195.8khz no-missing-codes guaranteed conditions v v ref- v dd ref+ input voltage range k 124 r ref reference resistance pf 32 c in _ input capacitance a 3 i in _ input leakage current v v ref- v ref+ v in _ input voltage range v/s 3.1 15 input slew rate, tracking lsb 1 tue total unadjusted error bits 8 n resolution mhz 1 input full-power bandwidth db 45 sinad signal-to-noise plus distortion ratio 45 lsb 1 dnl differential nonlinearity lsb 1 zero-code error lsb 1 full-scale error lsb 1/4 channel-to-channel mismatch units min typ max symbol parameter max11_m, f sample = 740khz, f in _ = 195.7khz max11_c/e, f sample = 1mhz, f in _ = 195.8khz db -50 thd total harmonic distortion -50 max11_m, f sample = 740khz, f in _ = 195.7khz max11_c/e, f sample = 1mhz, f in _ = 195.8khz db 50 sfdr spurious-free dynamic range 50 v gnd v ref+ ref- input voltage range accuracy (note 1) dynamic performance analog input reference input downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v 5%, ref+ = 5v, ref- = gnd, read mode (mode = gnd), t a = t min to t max , unless otherwise noted.) note 2: guaranteed by design. note 3: power-down current increases if logic inputs are no t driven to gnd or v dd . wr cs , rd , pwrdn , a0, a1, a2 a 3 i inh d0Cd7, rdy d0Cd7, rdy, digital outputs = 0v to v dd i source = 360a, int , d0Cd7 rdy, i sink = 2.6ma mode mode i sink = 1.6ma, int , d0Cd7 cs , wr , rd , pwrdn , a0, a1, a2 cs , wr , rd , pwrdn , mode, a0, a1, a2 cs , wr , rd , pwrdn , mode, a0, a1, a2 conditions input high current 1 pf 58 c out three-state capacitance (note 2) a 3 i lkg three-state current v 4 v oh output high voltage v 0.4 v ol output low voltage 0.4 pf 58 c in input capacitance (note 2) a 1 i inl input low current 50 200 v 3.5 v inh input high voltage mode 2.4 cs , wr , rd , pwrdn , a0, a1, a2 v units min typ max symbol parameter 1.5 v inl input low voltage 0.8 81 5 v 4.75 5.25 v dd supply voltage v dd = 4.75v to 5.25v, v ref = 4.75v cs = rd = v dd , pwrdn = 0v (note 3) lsb 1/16 1/4 psr power-supply rejection a 11 0 power-down v dd current cs = rd = 0v, pwrdn = v dd ma 82 0 i dd v dd supply current max11_c max11_e/m logic inputs logic outputs power requirements downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n 4 _______________________________________________________________________________________ timing characteristics (v dd = +4.75v, t a = +25c, unless otherwise noted.) (note 4) c l = 50pf c l = 50pf, r l = 5.1k to v dd c l = 100pf (note 5) t rd < t intl , (note 5) ns 50 80 t inth rd to int delay (rd mode) ns t crd + 50 t acc0 data-access time (rd mode) (note 7) (note 6) ns 160 t acq ns 70 t rdy cs to rdy delay ns 0 t csh cs to rd , wr hold time ns 0 t css cs to rd , wr setup time minimum acquisition time ns 60 ns 320 t up power-up time ns 700 t crd conversion time (rd mode) ns 660 t cwr conversion time (wr-rd mode) t dh data hold time 85 t crd + 65 185 85 0 0 70 370 875 90 t crd + 75 260 100 0 0 80 520 975 t a = t min to t max 100 75 35 610 pipelined mode, c l = 50pf c l = 50pf 185 t rd < t intl , c l = 100pf (note 5) 235 t rd < t intl , determined by t acc1 t rd > t intl , determined by t acc2 60 205 0.35 ns 80 t ihwr wr to int delay ns 65 t read2 rd pulse width (wr-rd mode) pipelined mode, c l = 100pf ns 30 t ah ns 380 500 t intl wr to int delay ns 150 t ri rd to int delay ns 185 t acc1 data-access time (wr-rd mode) multiplexer address hold time ns 45 ns 160 t read1 rd pulse width (wr-rd mode) s 0.25 t rd delay between wr and rd pulses s 0.25 10 t wr wr pulse width t id data-access time after int 0.28 10 120 85 40 700 220 275 70 240 0.45 0.4 10 110 t rd > t intl , c l = 100pf (note 5) ns 90 t acc2 data-access time (wr-rd mode) 130 note 4: input control signals are specified with t r = t f = 5ns, 10% to 90% of 5v, and timed from a voltage l evel of 1.6v. note 5: see figure 1 for load circuit. parameter defined as the time required for the output to cross 0.8v or 2.4v. note 6: see figure 2 for load circuit. parameter defined as the time required for the data lines to change 0.5 v. note 7: also defined as the minimum address-valid to conver t-start time. max11_c/e t a = +25c all grades conditions min max min max units min typ max symbol parameter max11_m c l = 20pf c l = 100pf 685 865 1125 downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n _______________________________________________________________________________________ 5 1.5 0.6 -60 140 conversion tim e vs. am bient tem perature 0.8 0.7 1.4 temperature (c) t crd (normalized to value at v dd = +5v, +25c) 20 1.1 1.0 0.9 -20 100 60 1.3 1.2 v dd = +4.75v v dd = +5v v dd = +5.25v max114/118-01 8.0 6.0 1k 10k 100k effective num ber of bits vs. input frequency (wr-rd m ode) input frequency (hz) effective number of bits 1m 7.5 7.0 6.5 max114/118-02 f sample = 1mhz v in = 4.96vp-p 0 0 400 signal-to-noise ratio -100 -80 -40 -20 frequency (khz) ratio (db) 300 -60 100 200 500 max114/118-04 sample frequency = 1mhz snr = 48.2db v dd = 4.75v input frequency = 195.8ksps v in = 4.72vp-p 50 0 100k average power consum ption vs. sam pling rate using pwrdn 10 40 sampling rate (conversions/sec) power dissipation (mw) 1k 20 30 10k 1m max114/118-03 5 6 0 75 100 150 175 250 total unadjusted error vs. power-up tim e 1 4 max114/118-06 power-up time, t up (ns) tue (lsb) 125 200 225 3 2 12 0 -60 supply current vs. tem perature (excluding reference current) 2 4 6 8 10 max114/118-08 temperature (c) supply current (ma) 60 100 140 -20 20 __________________________________________typic a l o pe ra t ing cha ra c t e rist ic s (v dd = +5v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n 6 _______________________________________________________________________________________ ___________________________________________________ ___________pin de sc ript ion three-state data outputs d1, d2, d3 7, 8, 9 three-state data output (lsb) d0 6 lower limit of reference span. ref- sets the zero-c ode voltage. range is gnd v ref- < v ref+ . ref- 13 ground gnd 12 read input. rd must be low to access data (see digital interface section). rd 10 write-control input/ready-status output (see digital interface section) wr /rdy 15 upper limit of reference span. ref+ sets the full-s cale input voltage. range is v ref- < v ref+ v dd . internally hard-wired to in8 (table 1). ref+ 14 multiplexer channel address input (msb) a2 three-state data output (msb) d7 20 positive supply, +5v v dd 24 pin mode selection input. internally pulled low with a 50a current source. mode = 0 acti- vates read mode; mode = 1 activates write-read mode (see digital interface section). mode 5 analog input channel 6 in6 function name power-down input. pwrdn reduces supply current when low. pwrdn 23 multiplexer channel address input (lsb) a0 22 multiplexer channel address input a1 21 analog input channel 7 in7 three-state data outputs d4, d5, d6 17, 18, 19 chip-select input. cs must be low for the device to recognize wr or rd inputs. cs 16 9, 10, 11 8 14 12 17 16 23 22 27 7 1 26 25 24 28 19, 20, 21 18 max114 max118 analog input channel 5 in5 2 analog input channel 2 in2 3 analog input channel 1 5 in1 4 6 analog input channel 4 in4 1 analog input channel 3 3 in3 2 4 15 interrupt output. int goes low to indicate end of conversion (see digital interface section). 11 int 13 downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n _______________________________________________________________________________________ 7 _______________de t a ile d de sc ript ion conve rt e r ope ra t ion the max114/max118 use a half-flash conversion tech- nique (see functional diagram ) in which two 4-bit flash adc sections achieve an 8-bit result. using 15 com- parators, the flash adc compares the unknown input voltage to the reference ladder and provides the up per four data bits. an internal digital-to-analog conve rter (dac) uses the four most significant bits (msbs) to generate both the analog result from the first flas h con- version and a residue voltage that is the differenc e between the unknown input and the dac voltage. the residue is then compared again with the flash com- parators to obtain the lower four data bits (lsbs). an internal analog multiplexer enables the devices to read four (max114) or eight (max118) different anal og voltages under microprocessor (p) control. one of the max118s analog channels, in8, is internally hard- wired and always reads v ref+ when selected. pow e r-dow n m ode in burst-mode or low sample-rate applications, the max114/max118 can be shut down between conver- sions, reducing supply current to microamp levels ( see typical operating characteristics ). a logic low on the pwrdn pin shuts the devices down, reducing supply current typically to 1a when powered from a single +5v supply. a logic high on pwrdn wakes up the max114/max118, and the selected analog input enters the track mode. the signal is fully acquired after 360ns (this includes both the power-up delay and the trac k/hold acquisition time), and a new conversion can be star ted. if the power-down feature is not required, connect pwrdn to v dd . for minimum current consumption, keep digital inputs at the supply rails in power-down mo de. refer to the reference section for information on reduc- ing reference current during power-down. ___________________digit a l i nt e rfa c e the max114/max118 have two basic interface modes, which are set by the mode pin. when mode is low, the converters are in read mode; when mode is high, the converters are set up for write-read mode. the a0, a1, and a2 inputs control channel selection, as sho wn in table 1. the address must be valid for a minimum time, t acq , before the next conversion starts. re a d m ode (m ode = 0 ) in read mode, conversions and data access are con- trolled by the rd input (figure 3). the comparator inputs track the analog input voltage for the durat ion of t acq . initiate a conversion by driving cs and rd low. with ps that can be forced into a wait state, hold rd low until output data appears. the p starts the co nver- sion, waits, and then reads data with a single read instruction. data outputs data outputs c l r l = 3k c l a) high-z to v oh b) high-z to v ol r l = 3k v dd figure 1. load circuits for data-access time test data outputs 10pf 3k 10pf a) v oh to high-z b) v ol to high-z 3k v dd data outputs figure 2. load circuits for data-hold time test in2 in1 01 selected channel in4 in3 11 10 in6 in5 in8 (reads v ref+ if selected) in7 max114 00 table 1. truth table for input channelselection 001 011 010 101 111 110 100 max118 000 a2 a1 a0 a1 a0 downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 in read mode, wr /rdy is configured as a status output (rdy), so it can drive the ready or wait input of a p. rdy is an open-collector output (no internal pull-u p) that goes low after the falling edge of cs and goes high at the end of the conversion. if not used, the wr /rdy pin can be left unconnected. the int output goes low at the end of the conversion and returns high on th e ris- ing edge of cs or rd . writ e -re a d m ode (m ode = 1 ) figures 4 and 5 show the operating sequence for wri te- read mode. the comparator inputs track the analog input voltage for the duration of t acq . the conversion is initiated by a falling edge of wr . when wr returns high, the result of the four-msbs flash is latched into the output buffers and the conversion of the four-lsbs flash starts. int goes low, indicating conversion end, and the lower four data bits are latched into the output bu ffers. the data is then accessible after rd goes low (see timing characteristics ). a minimum acquisition time (t acq ) is required from int going low to the start of another conversion ( wr going low). options for reading data from the converter include using internal delay, reading before delay, and pip elined operation (discussed in the following sections). u sing i nt e rna l de la y the p waits for the int output to go low before reading the data (figure 4). int goes low after the rising edge of wr , indicating that the conversion is complete and th e result is available in the output latch. with cs low, data outputs d0Cd7 can be accessed by pulling rd low. int is then reset by the rising edge of cs or rd . fa st e st conve rsion: re a ding be fore de la y figure 5 shows an external method of controlling th e conversion time. the internally generated delay (t intl ) varies slightly with temperature and supply voltage , and can be overridden with rd to achieve the fastest conversion time. rd is brought low after the rising edge of wr , but before int goes low. this completes the conversion and enables the output buffers that cont ain the conversion result (d0Cd7). int also goes low after the falling edge of rd and is reset on the rising edge of rd or cs . the total conversion time is therefore: t wr + t rd + t acc1 = 660ns. +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n 8 _______________________________________________________________________________________ t ah t acq t dh t read2 t rd d0d7 rd wr cs int valid data (n) t intl t acc2 t wr t css t csh t acq t css t csh a0a2 t inth address valid (n) address valid (n + 1) figure 4. write-read mode timing (t rd > t intl ) (mode = 1) t css t acq t dh t read1 t rd t intl t acq t ah rd wr cs int valid data (n) t css t csh t inth t wr t csh t acc1 t cwr t ri a0a2 d0d7 address valid (n) address valid (n + 1) figure 5. write-read mode timing (t rd < t intl ) (mode = 1) t css t rdy t acq t ah with external pull-up t csh t acq t inth t up t dh t crd t acco d0d7 rdy rd cs pwrdn int a0a2 valid data (n) address valid (n + 1) address valid (n) t ah figure 3. read mode timing (mode = 0) downloaded from: http:///
pipe line d ope ra t ion besides the two standard write-read-mode options, pipelined operation can be achieved by connecting wr to rd (figure 6). with cs low, driving wr and rd low initiates a conversion and concurrently reads t he result of the previous conversion. _____________ana log conside ra t ions re fe re nc e figures 7a, 7b, and 7c show typical reference conne c- tions. the voltages at ref+ and ref- set the adcs analog input range (see figure 10). the voltage at ref- defines the input that produces an output code of a ll zeros, and the voltage at ref+ defines the input th at produces an output code of all ones. the internal resistance from ref+ to ref- can be as low as 1k , and current will flow through it even when the max114/max118 are shut down. figure 7d shows how an n-channel mosfet can be connected to ref- m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n _______________________________________________________________________________________ 9 ref- v dd in_ ref+ v in+ v in- gnd +5v 0.1 m f 4.7 m f max114 max118 figure 7a. power supply as reference ref- v dd mx584 in_ ref+ v in+ v in- gnd +5v c1 0.1f 0.1f 4.7f max114 max118 figure 7b. external reference, 4.096v full scale ref- ref+ 0.1f 0.1f * current path must still exist from v in- to gnd r* in_ v in- v dd v in+ gnd +5v +2.5v 4.7f 0.1f max114 max118 figure 7c. input not referenced to gnd ref- v dd max874 ref+ +5v 0.1f 0.1f c1 3.3f pwrdn pwrdn n-fet* * irml2402 max114 max118 figure 7d. an n-channel mosfet switches off the re ference load during power-down t acq t intl rd, wr int new data (n) t wr t acq t ah t csh t ihwr t css t id old data (n - 1) d0d7 address valid (n) address valid (n + 1) a0a2 cs figure 6. pipelined mode timing ( wr = rd ) (mode = 1) downloaded from: http:///
m ax 1 1 4 /m ax 1 1 8 to break this current path during power-down. the f et should have an on-resistance of less than 2 with a 5v gate drive. when ref- is switched, as in figure 7d, a new conversion can be initiated after waiting a per iod of time equal to the power-up delay (t up ) plus the n- channel fets turn-on time. although ref+ is frequently connected to v dd , the cir- cuit of figure 7d uses a low-current, low-dropout, 4.096v voltage reference: the max874. since the max874 cannot continuously furnish enough current f or the reference resistance, this circuit is intended for applications where the max114/max118 are normally in standby and are turned on in order to make mea- surements at intervals greater than 65s. c1 (the capacitor connected to ref+) is slowly charged by t he max874 during the standby period, and furnishes the reference current during the short measurement peri od. c1s 3.3f value ensures a voltage drop of less tha n 1/2lsb when performing four to eight successive con - versions. larger capacitors reduce the error still further. use ceramic or tantalum capacitors for c1. i nit ia l pow e r-u p when power is first applied, perform a conversion t o ini- tialize the max114/max118. disregard the output dat a. bypa ssing use a 4.7f electrolytic in parallel with a 0.1f c eramic capacitor to bypass v dd to gnd. minimize capacitor lead lengths. bypass the reference inputs with 0.1f capacitors, as shown in figures 7a, 7b, and 7c. ana log i nput s figure 8 shows the equivalent circuit of the max114 / max118 input. when a conversion starts and wr is low, v in_ is connected to sixteen 0.6pf capacitors. during this acquisition phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches. in addition, about 22 pf of stray capacitance must be charged. the input can be modeled as an equivalent rc network (figure 9). as source impedance increases, the capacitors take longer to charge. the typical 32pf input capacitance allows source re sis- tance as high as 800 without setup problems. for larger resistances, the acquisition time (t acq ) must be increased. internal protection diodes, which clamp the analog input to v dd and gnd, allow the channel input pins to swing from gnd - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, limit the input current to no more than 2ma, as excessive current will degrade the conversion accuracy of the on channel. track/hold the track/hold enters hold mode when a conversion starts ( rd low or wr low). int goes low at the end of the conversion, at which point the track/hold enter s track mode. the next conversion can start after the min- imum acquisition time, t acq . +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n 10 ______________________________________________________________________________________ 2k r in v in_ 22pf v in max114 max118 10pf figure 9. rc network equivalent input model r on r in v in2 max114 max118 . . . t/h mux figure 8. equivalent input circuit downloaded from: http:///
transfer function figure 10 shows the max114/max118s nominal trans- fer function. code transitions occur halfway betwee n successive-integer lsb values. output coding is bin ary with 1lsb = (v ref+ - v ref- ) / 256. conve rsion ra t e the maximum sampling rate (f max ) for the max114/ max118 is achieved in write-read mode (t rd < t intl ), and is calculated as follows: where t wr = the write pulse width, t rd = the delay between write and read pulses, t ri = rd to int delay, and t acq = minimum acquisition time. signa l-t o-n oise ra t io a nd effe c t ive n um be r of bit s signal-to-noise plus distortion (sinad) is the rati o of the fundamental input frequencys rms amplitude to all other adc output signals. the output spectrum is li mit- ed to frequencies above dc and below one-half the adc sample rate. the theoretical minimum analog-to-digital noise is caused by quantization error, and results directly from the adcs resolution: snr = (6.02n + 1.76)db, wher e n is the number of bits of resolution. therefore, a per- fect 8-bit adc can do no better than 50db. the fft plot (see typical operating characteristics ) shows the result of sampling a pure 195.8khz sinuso id at a 1mhz rate. this fft plot of the output shows t he output level in various spectral bands. the effective resolution (or effective number of b its) the adc provides can be measured by transposing the equation that converts resolution to snr: n = (sin ad - 1.76) / 6.02 (see typical operating characteristics ). t ot a l h a rm onic dist ort ion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal (in the fr equency band above dc and below one-half the sample rate) t o the fundamental itself. this is expressed as: where v 1 is the fundamental rms amplitude, and v 2 through v n are the amplitudes of the 2nd through nth harmonics. spurious-fre e dyna m ic ra nge spurious-free dynamic range (sfdr) is the ratio of the fundamental rms amplitude to the amplitude of the next largest spectral component (in the frequency band above dc and below one-half the sample rate). usually the next largest spectral component occurs at some harmonic of the input frequency. however, if t he adc is exceptionally linear, it may occur only at a ran- dom peak in the adcs noise floor. see the signal-t o- noise ratio graph in typical operating characteristics . thd = 20log v v v ...v v 2 2 3 2 4 2 n 2 1 +++ ? ? f= 1 t + t + t + t f 1 250ns 250ns 150ns 160ns f 1.23mhz max wr rd ri acq max max = +++ = m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n ______________________________________________________________________________________ 11 output code input voltage (lsbs) fs fs - 1lsb full-scale transition 123 11111111 11111110 11111101 00000011 00000010 00000001 00000000 1lsb = v ref+ - v ref- 256 v ref- v ref+ figure 10. transfer function downloaded from: http:///
maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1996 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. m ax 1 1 4 /m ax 1 1 8 +5 v, 1 m sps, 4 & 8 -cha nne l, 8 -bit adcs w it h 1 a pow e r-dow n maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. 12 __________________m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , sunnyva le , ca 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0 ? 1996 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. __orde ring i nform a t ion (c ont inue d) ___________________________________________________ _______pin configura t ions ___________________chip i nform a t ion 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 in7 v dd pwrdn a0 a1 a2 ref- d7 d6 d5 d4 cs wr/rdy ref+ gnd int rd d3 d2 d1 d0 mode in1 in2 in3 in4 in5 in6 dip/ssop max118 transistor count: 2011 *dice are specified at t a = +25c, dc parameters only. **contact factory for availability. part max118 cpi max118cai max118c/d 0c to +70c 0c to +70c 0c to +70c temp. range pin-package 28 wide plastic dip 28 ssop dice* max118epi MAX118EAI max118mji -55c to +125c -40c to +85c -40c to +85c 28 wide plastic dip 28 ssop 28 wide cerdip** 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 v dd pwrdn a0 a1 in1 in2 in3 in4 top view d7 d6 d5 d4 d2 d1 d0 mode 16 15 14 13 9 10 11 12 cs wr/rdy ref+ ref- gnd int rd d3 dip/ssop max114 downloaded from: http:///

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